The present disclosure relates to computer systems, and more specifically, to a microarchitecture based solution for hardware controlled dynamic enhancement of thread instruction fetch rates on a simultaneous multithreading processor.
Computer executable instruction belonging to a computer program may be allocated to, and executed in, individual threads of a computer system. Computer processor resources for executing the program instructions in each thread may be allocated amongst the executing threads of a computing system based on a thread hierarchy informed by a priority assigned to each thread. Processors may execute the program instructions included in each thread in sequences informed by the structure of the computer programs issuing the instructions. Some computer processors may execute these program instructions in a different order than the order indicated by the computer program by making speculations as to which execution path the computer program will follow, or which instructions should be executed, in the future. This hardware speculation may influence the instruction throughput of, or the rate at which instructions are executed by, processors.